Description of the Prior Art
The basic structure and operational characteristic of a static induction transistor (SIT) are first explained. FIG. 1 (a) shows a sectional view of a vertical (thicknesswise of a substrate) junction gate type SIT and the potential distribution therein.
The SIT comprises a source n.sup.+ region 101 (impurity concentration N=10.sup.17 -10.sup.20 cm.sup.-3), a drain n.sup.+ region 102 (N=10.sup.17 -10.sup.20 cm.sup.-3), a gate n.sup.+ region 103 (N=10.sup.17 -10.sup.20 cm.sup.-3) and an epitaxially grown channel n region 104 (N=10.sup.12 -10.sup.17 cm.sup.-3). It has a smaller channel dimension and a lower impurity concentration in the channel area than an FET. Thus, under a zero gate bias condition or when a slight backward voltage is applied to the gate, a depletion layer 110 spreads as shown in FIG. 1 (d) and the device is pinched off.
At this time, a saddle-shaped potential barrier 105 as shown in FIG. 1 (b) appears in front of the source n.sup.+ region 101. The height of the potential barrier 105 controls the flow rate of carriers which mainly flow from the source to the drain over the potential barrier. Since the potential barrier 105 functions essentially as a gate, it is also called an "intrinsic gate" and the region in which the potential barrier 105 exists is called an "intrinsic gate region" 107.
Since the channel impurity concentration is low, the depletion layer 110 spreads with a small voltage applied across the gate and the drain as shown in FIG. 1 (e) so that the entire channel can be readily occupied by the depletion layer.
If the drain voltage is further increased, the height of the potential barrier (which is also a pinch-off potential) which controls the flow rate of the carriers is reduced and the barrier position (pinch-off point) moves toward the source. As a result, the quantity of carriers which are moved over the barrier increases and the drain voltage rises and the drain current increases to exhibit a current nonsaturation characteristic (Japanese Examined Patent Publication Nos. 52-77720 and 56-19749).
The above phenomenon which is inherent to the SIT, that is, (1) the channel pinch-off occurs without regard to the drain region and (2) the entire channel region is covered by the depletion layer, and is defined as reach-through. (This indicates that the depletion area spreads over the entire region and finally reaches the drain.) A characteristic of the reach-through is that the gate directly controls the saddle-shaped potential barrier and the drain controls the potential barrier through a coupling capacitance.
The carriers which flow from the source to the drain over the saddle-shaped potential barrier are concentrated into a center 106 of the channel.
FIG. 1 (c) shows the potential distribution of the SIT. (Potential distributions as viewed along broken lines A and B of FIG. 1 (a) correspond to A' and B' in FIG. 1 (c).) The coordinate at the center of the source is represented by (0, 0) and the Y-axis is defined from the source to the drain. The gate exists at Y=Y.sub.G along the X-axis, and a gate voltage is applied at X=.+-.X.sub.G. The drain exists at Y=Y.sub.D and the source exists at Y=0. The depletion layer extends from Y.sub.G to Y.sub.s toward the source and to Y.sub.d toward the drain.
Since the junction gate type SIT is normally on, it is disadvantageous in an integrated circuit. Thus, the channel is normally pinched off only by a diffusion potential in the gate P.sup.+ region 103, and a forward voltage is applied to the gate to cancel the diffusion potential to supply a current into the channel so that a normally-off operation is attained. However, in such forward operation, holes are injected below the gate P.sup.+ region 103 and a storage effect takes place. As a result, high speed operation is restricted.
In order to maintain the basic characteristic of the SIT and eliminate the minority carrier (hole) storage effect, an SIT having an insulated gate has been proposed (Japanese Unexamined Patent Publication No. 53-146577).
FIG. 2 (a) shows a sectional view of a lateral (along the substrate surface) insulate gate SIT. The SIT comprises a P substrate 201 (N=10.sup.12 -10.sup.17 cm.sup.-3), a source n.sup.+ region 202 (N=10.sup.17 -10.sup.20 cm.sup.-3) formed thereon, a drain n.sup.+ region 203 (N=10.sup.17 -10.sup.20 cm.sup.-3) and a gate electrode 204 formed on an insulation layer 205. The gate electrode 204 does not reach the top of the source n.sup.+ region 202 as opposed to a conventional MOS FET, so that the surface potential in the vicinity of the source n.sup.+ region 202 is set lower than those in other regions and it functions as a barrier to the electrons which flow through the inversion layer from the source to the drain. It is the height of the barrier that controls the quantity of electrons to be injected into the drain inversion layer 210 from the source.
If the distance L.sub.SG between the source and the gate of the insulated gate type SIT is short, a current nonsaturation characteristic will readily appear, but since the current flows through a surface channel of the inversion layer 210, the influence of the interface is large and it is not an ideal one from the standpoints of speed and noise characteristics. When the drain voltage increases, the punch-through by the depletion layer occurs as shown in FIG. 2 (b) and a punch-through current flows as shown by the arrow 62 and control by the saddle-shaped potential barrier is lost. The punch-through is defined as the spread of the depletion layer 211 of the drain region due to the drain region potential such that it contacts to the depletion layer of the source region in a wide area and the saddle-shaped potential barrier is no longer dominant.
A first problem to be resolved in the prior art insulated gate type SIT is the elimination of the punch-through.
The nonsaturation characteristic of the drain current versus drain voltage which is also a characteristic of the prior art SIT is due to the fact that the height of the saddle-shaped potential barrier of the intrinsic gate region depends on both the gate voltage and the drain voltage, but it has a disadvantage in that a voltage gain is hard to attain. The gain A.sub.V per stage of an amplifier is given by ##EQU1## where g.sub.m =(.rarw.I.sub.D /.rarw.V.sub.G): mutal conductance
r.sub.D =1/(.rarw.I.sub.D /.rarw.V.sub.D): drain internal resistance PA0 R.sub.L : load resistance PA0 I.sub.D : drain current PA0 V.sub.G : gate voltage PA0 V.sub.D : drain voltage PA0 B=[{(R.sub.1 +R.sub.2)(R.sub.3 +R.sub.4)-.alpha..sub.1 R.sub.1 (R.sub.3 +R.sub.4)-.alpha..sub.2 R.sub.3 (R.sub.1 +R.sub.2)}] PA0 L.sub.D : diffusion length PA0 .epsilon.: dielectric constant V.sub.DB =V.sub.D -V.sub.B +V.sub.bi PA0 N.sub.A : acceptor concentration of p substrate PA0 q: quantity of charge per unit area PA0 V.sub.bi : built-in potential of drain junction PA0 V.sub.B : substrate bias PA0 V.sub.FB : flat band voltage PA0 V.sub.C : channel voltage PA0 [1] Elimination of punch-through; PA0 [2] Elimination of hot carriers; PA0 [3] Obtaining saturation characteristic without increasing r.sub.s ; that is, without depending on the feedback effect; and PA0 [4] Latch-up in the complementary circuit.
The larger the r.sub.D, that is, the higher the degree of the saturation characteristic, the higher is the voltage gain.
However, when the saturation characteristic is realized by a negative feedback effect due to the source internal resistance r.sub.s (see H. Tango et al: Solid State Electronics, Vol. 13 p. 139, Oct. 1970) as is done in a conventional FET, an apparent mutual conductance gm' is observed (In the past, it has been misunderstood as a mutual conductance of the FET.) ##EQU2## If r.sub.s is large, the saturation characteristic is attained but the gm' is apparently smaller than the gm which is attained by the intrinsic gate.
So far, a principle to realize the saturation characteristic while maintaining the high gm and the high speed attained in the nonsaturation type insulated gate SIT and without increasing r.sub.s (that is, without depending on the feedback effect), has not been proposed.
If the saddle-shaped potential barrier of the SIT can be controlled only by the gate electrode, design of a multi-stage amplifier circuit will be facilitated.
Accordingly, a second problem to be resolved in the prior art insulated gate type SIT is realization of the intrinsic saturation characteristic in the insulated gate type SIT.
When an integrated circuit is to be constructed by using the insulated gate type SIT, a complementary circuit which is advantageous in density, microminiaturization, ease of design and power consumption will be a main component. However, when the microminiaturization is carried out with the complementary MOSFET (C-MOS), there are several problems, and when the complementary structure is used in the insulated gate type SIT, those problems must be resolved.
A typical C-MOS inverter is shown in FIG. 3 (a). A p well region 302 is formed on an n substrate 301, and a source P.sup.+ region 303, a drain P.sup.+ region 304 and an insulated gated electrode 305 on the n substrate 301 form a PMOS (p-channel MOSFET), and a source n.sup.+ region 306, a drain n.sup.+ region 307 and an insulated gate electrode 308 on the p well region 302 form an nMOS (n-channel MOSFET). The gate electrodes 305 and 308 are interconnected to provide an input terminal, and the drain p.sup.+ region 304 and the drain n.sup.+ region 307 are interconnected to provide an output terminal. The source p.sup.+ region 303 is adjacent to a channel stopper n.sup.+ region 309 which also sets the potential of the p substrate 301, and a voltage V.sub.DD is applied to the source p.sup.+ region 303. The source n.sup.+ region 306 is adjacent to a channel stopper p.sup.+ region 310 which also sets the potential of the p well 302. A voltage V.sub.SS is applied to the source n.sup.+ region 306 (V.sub.DD &gt;V.sub.SS).
In order to achieve the high density and the microminiaturization of such CMOS-FET, it is necessary to overcome the following three problems.